RNN (5) - FPGA System Design

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This is the last post on hardware implementation. The RTL codes of the previous post were designed for HW Accelerator IP to perform RNN, and this post describes how to design the whole system for targetting FPGA. The FPGA board used here is an FPGA Board using Xilinx ZYNQ-7000 as open hardware called Pynq-z2. (For Pynq-z2, please refer to the link below.)


- http://www.pynq.io/

- https://www.tulembedded.com/FPGA/ProductsPYNQ-Z2.html

- https://pynq.readthedocs.io/en/latest/


First, the RNN Accelerator must open a channel to communicate with the ARM-Cortex A9 where SW is running. IP Packaging is performed using Vivado of Xilinx, and I used the AXI interface template provided by Vivado. RTL codes on the right of the figure below in the code window shows how to combine RNN IP with AXI interface. IP Packaging is possible easily through a few steps in Vivado. (Details will be posted separately.)


After IP Packaging, you need to create a bit file to download to the Pynq-z2 board. The figure below shows the HW Block diagram to be downloaded to the Pynq-z2 board. The block named  wave_predictor in the upper right corner shows RNN IP. After synthesizing the whole, place and route, the bitfile is finished. After P&R, you need to look closely at the timing report to see if there is any violation. If there is no timing violation and it proceeds without any problems, you can download the following three files to the board. (Most of these can be done easily in the Vivado tool, but I will post related posts separately.)


source: https://github.com/bxk218/RNN_wave_predictor_verilog/tree/main/rtl/vivado/overlay/upload

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